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- Education
- Ph.D. Electrical Engineering, University of Texas at Austin, anticipated 2009
- M.S. Electrical Engineering, Brigham Young University, August 2005
- B.S. Computer Engineering, Brigham Young University, April 2003
- Honors
- University of Texas Microelectronics and Computer Development Fellowship
- University of Texas Engineering Department Multi-year PhD Fellowship
- Honorable Mention, NSF Graduate Research Fellowship
- Rocky Mountain NASA Space Grant Fellowship Recipient
- Full Tuition Undergraduate Heritage Scholarship, Brigham Young University
- National Merit Finalist
- High school Valedictorian
- Eagle Scout
- Work Experience
- The University of Texas at Austin - Research Assistant - Jan 2006-present
- datamining and machine learning for computer architecture optimization
- contributing to the FAST infrastructure
- researched control speculation in data-flow architectures
- IBM Austin Research Laboratory - Summer Intern - Summer 2007
- investigated machine learning techniques for branch prediction
- Los Alamos National Laboratory - Summer Intern - Summer of 2002, 2003, and 2005
- developed an algorithm for a non-coherent CDMA receiver, along with a working FPGA implementation
- created Matlab tools for modeling quantization effects, automatically generating VHDL testbenches, and verifying a match between a Matlab and VHDL model
- created software/hardware tools to control and collect data from an FPGA for use in radiation testing with a proton accelerator
- analyzed and correlated accelerator results with fault injection tool results
- Brigham Young University - Research Assistant - Feb 2001-April 2005
- researched FPGA reliability - see http://reliability.ee.byu.edu
- developed tools to perform TMR at the EDIF level for FPGA fault tolerance
- created a fault injection tool for emulating SEU behavior in the configuration memory of SRAM-based FPGAs
- Publications
- Please refer to the publications page.
- Projects
- FPGA implementation of a software radio. Constructed a bit-accurate model of a QPSK receiver using Matlab and Java. Used VHDL to implement the design and verified design behavior using VHDL testbenches.
- Datapath synthesis for minimizing hardware under a throughput constraint. Created a Java-based synthesis tool to perform scheduling and binding on a directed graph. The tool chooses from amongst bit-serial, parallel and pipelined variations of operators in order to minimize circuit area while meeting a throughput constraint.
- Skills
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- Ruby
- VHDL
- Java
- C/C++
- Objective-C
- lex/yacc
- MPI, OpenMP
- PHP, MySQL
- HTML, CSS
- Matlab, MEX
- Simulink
- SystemC, HandelC
- Xilinx FPGA Tools
- Technical writing
- Computer arithmetic
- Computer architecture
- Graph theory
- Digital design
- Linux, sysadmin
- Mac OS X
- CVS, SVN